1. Field of the Invention
The present invention relates to a method for driving a plasma display panel (PDP) and a plasma display device for displaying an image utilizing a plasma display panel. The present invention is useful for increasing an addressing speed.
In a display utilizing an AC type plasma display panel, an addressing process is performed for forming an appropriate quantity of wall charge only in cells to be lighted among cells that are arranged in a matrix, and after that a sustaining process is performed for generating display discharge plural times in accordance with a luminance value utilizing the wall charge. The time necessary for the addressing process is proportional to the number of rows of a display screen (i.e., a resolution in the vertical direction). Therefore, the higher the resolution becomes, the shorter the period becomes that can be assigned to display discharge out of the frame period. In addition, the possible number of frame division for a gradation display becomes small. It is desirable to shorten the time necessary for the addressing process as much as possible when increasing the number of display discharge times for improving luminance or increasing the number of frame division for enhancing gradation property.
2. Description of the Prior Art
In a plasma display panel having an n×m matrix display screen, line-sequential addressing is performed by scan electrodes for selecting a row and data electrodes for selecting a column. In a one-frame display, an address period that is assigned to addressing is divided equally to all scan electrodes. Each of the scan electrodes becomes active by being biased to a predetermined selecting potential only during one row selection period. Usually, an order of selecting a row is an arrangement order, and the scan electrode to be active is switched from one side to the other side of the arrangement. In synchronization with this row selection, display data of all columns of the selected row are outputted from the data electrodes in each row selection period. In other words, in accordance with display data, potential values of all data electrodes are controlled at a time. The display data are usually binary data (1 or 0) that indicate whether a cell is lighted or not, and the potential control of the data electrode is also a binary control of whether address discharge is generated or not. If the address discharge is generated in the cell to be lighted, it is called a write form. If the address discharge is generated in the cell not to be lighted, it is called an erase form.
FIGS. 14A and 14B are timing charts of row selection and data output in the conventional method. In FIGS. 14A and 14B, timings of row selection and data output concerning three rows having arrangement orders of 1–3 are shown. The form shown in FIG. 14A is the most typical form in which the row selection is done by shifting the time completely for each row. In this form, the time necessary for addressing one screen is the product of the row selection period and the number of rows. For example, when the row selection period is three microseconds, the number of rows is 480, and the number of subfields (screens) that constitute one field of an interlace display is eight, the time necessary for the addressing process is 11.52 milliseconds, so most portion of the field period (16.7 milliseconds) is consumed for the addressing process. The form shown in FIG. 14B is disclosed in Japanese unexamined patent publication No. 2001-51649, in which row selection periods overlap each other for high speed addressing. In the plasma display panel, there is a phenomenon that discharge begins when some time passes after a cell voltage exceeds a discharge start voltage (a discharge delay). Therefore, some overlap in the row selection does not make any harm to the addressing process. Also in the addressing process shown in FIG. 14B, data output for each row is performed after harmonizing the row selection and the period similarly to the addressing process shown in FIG. 14A. Namely, in the addressing process shown in FIG. 14B, data outputs for two rows also overlap each other by the time equal to the overlapping time of the row selection.
As explained above, the row selections are overlapped with each other so that the time necessary for the addressing process can be shortened. Concerning the row selection, scan electrodes corresponding to the first and the second rows that overlap each other may be driven by different drivers. Here, the number of electrodes that can be handled by a driver made of an integrated circuit is approximately a few tens. Therefore, a few to a few tens of drivers are used for driving scan electrodes whose number is more than a few hundreds in a plasma display panel. Accordingly, when the scan electrodes of two rows overlapping in the row selection are connected to different drivers, the overlapping in the row selection can be realized by using a driver having the same structure as the case of non-overlap.
However, the conventional driving method, in which the row selection is overlapped as shown in FIG. 14B and the start and the end of data output correspond to the row selection, has a problem that is the necessity of a driving circuit having a complicated structure. Namely, since display data of two different rows are outputted with overlapped in the time scale with each other for one data electrode before the overlap in the row selection, a circuit is necessary that memorizes display data of two rows and calculates the logical OR of these data. A driver for a data electrode that is used in the case where the row selection is not overlapped cannot be used without any change.